In modern integrated circuits, the number and density of individual circuit elements, such as field effect transistors, is steadily increasing and, as a consequence, performance of these integrated circuits is currently improving. The increase in package density and signal performance of integrated circuits requires the reduction of critical feature sizes, such as the gate length and the channel length of field effect transistors, to minimize the chip area occupied by a single circuit element and to reduce signal propagation delay resulting from a delayed channel formation. However, currently critical feature sizes are approaching 0.1 μm and less and a further improvement in circuit performance by reducing the sizes of the transistor elements is partially offset by parasitic capacitances of the transistors formed in bulk silicon substrates.
To meet the ever-increasing demands with respect to device and circuit performance, circuit designers have proposed new device architectures. One technique to improve performance of a circuit, for example of a CMOS device, is to fabricate the circuit on a so-called silicon-on-insulator (SOI) substrate, as illustrated to the left of line 101 in FIG. 1. An SOI substrate comprises an insulating layer 103 formed on a bulk substrate 105, for example, a silicon substrate. The insulating layer is generally formed of silicon dioxide and is sometimes referred to as a buried oxide layer or “box” layer. Bulk substrate 105 is typically P-doped. An active silicon layer 107 is formed on the insulating layer. Active regions 109 for a field effect transistor device, defined by shallow trench isolation structures 111, are formed in active silicon layer 107. For an N-MOS transistor, the active regions 109 (the source and drain of the transistor) are N-doped and the region 113 between active regions 109 is P-doped. Further, a gate electrode 115, e.g., of polysilicon, formed on a gate insulation layer 117, and sidewall spacers 119, on both sides of the gate electrode, are formed on region 113 of active silicon layer 107. The resulting transistor is entirely electrically isolated from the regions surrounding the transistor area. Contrary to a conventional device formed on a bulk semiconductor substrate, the isolation of the active region of the SOI device significantly suppresses parasitic effects known from conventional devices, such as latch-up and leakage currents drifting into the substrate. SOI devices are also characterized by lower parasitic capacitances compared to devices formed on a bulk semiconductor substrate and, hence, exhibit an improved high-frequency performance. Moreover, due to the significantly reduced volume of the active region, radiation-induced charge carrier generation is also remarkably reduced thereby rendering SOI devices extremely suitable for applications in radiation-intensive environments.
However, it is also well known that during operation undesirable charges may accumulate below the channel region of the transistor, thereby adversely affecting the transistor characteristics, such as the threshold voltage, single-transistor-latch-up, and the like.
Furthermore, undesirable charge damage on devices may also occur during the course of fabricating such SOI structures. For example, the use of plasma-based etching processes may result in undesirable charge damage to components of the SOI device, such as the gate insulation layer.
A conventional approach to the problem of charge damage entails the formation of a substrate N+ diode to protect plasma process charging for SOI devices connected to a non-VSS node, as shown to the right of line 101 in FIG. 1. Specifically, an N+ contact 121 is formed in P-doped substrate 105 and connected to the SOI device via conductive contacts 123 and 125 and metal line 127 (with inter layer dielectric 129 insulating the transistor from metal line 127). However, it was found that such an approach engenders implementation problems due to poor N+ junction diode properties or to interaction with substrate properties and connections. In addition, as the design creates a virtual VSS node which is higher than VSS, a P+ substrate contact lightning rod approach fails to provide appropriate charging protection for the SOI device.
A need therefore exists for efficient methodology and device providing plasma charging protection for SOI devices which are connected to a non-VSS circuit node, particularly for advanced technology designs and beyond.